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For Communications Equipment
MN86062
CODEC LSI for Facsimile Images
Overview
The MN86062 is a high-speed LSI codec for compressing and decompressing images using the MH, MR, and MMR standard compression methods specified in the ITU-T T.4 and T.6 recommendation. Registers and other settings provide flexible support for a variety of processing.
Features
Compression methods MH, MR, and MMR Operating mode: Page mode Bus configuration: Choice of dual- or single-bus operation Decoding error processing: Choice of replacing with the previous line or a white line Image bus configuration: 8 bits, maximum 16 megabytes address space of image bus, 2-channel master DMA System bus configuration: X80 interface compatible, 8 bits, 2-channel slave DMA Pixels per line: maximum 64K, in byte increments Concurrent DMA transfers over image bus and command processing Support for pointer management for image buffer Wide selection of independent parameters for coding, decoding, transfers between buses, and DMA transfersr Support for time-shared processing by line for both coding and decoding
Applications
Facsimile equipment
MN86062
Pin Assignment
For Communications Equipment
VSS2 VDD2 TACK VSS3 VDD3 N.C.3 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 VDD4 VSS4 TEST2 TEST1 TEST0 NACKD NACKC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
N.C.1 N.C.2 IA18 IA17 IA16 IA15 IA14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
IA19 IA20 IA21 IA22 IA23 NDCMP NDEND NDACK1 NDACK0 NDREQ1 NDREQ0 NIDACK IR/W NIAEN NDRUN NIBACK NIBREQ 2SYSCLK VDD1 VSS1 SYSCLK
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
TEST3 TEST4 D0 D1 D2 D3 D4 D5 D6 D7 NIRQ NRESET A0 A1 A2 A3 NCS NRD NWT NREQC NREQD
(TOP VIEW) QFP084-P-1818
Microprogram control block IA(23:0) System bus interface Main sequencer Sub sequencer Image bus interface ID(7:0) 51 IR/W 50 52 47 ALU1 Register bank Parameter register 53 55 54 Slave DMA (2 channels) Table look-up block Mode selection block Master DMA (2 channels) 56 NDACK1 49 57 58 Coding FIFO Coding table Change point detector Coding line FIFO Image reconstruction block Reference line FIFO NDRUN NDEND NDCMP NDREQ0 NDACK0 NDREQ1 ALU2 48 NIAEN NIDACK NIBREQ NIBACK
Block Diagram
A(3:0)
D(7:0)
NCS
NRD
25
NWT
24
32
NIRQ
For Communications Equipment
NRESET
31
2SYSCLK
46
SYSCLK
43
NREQC
23
NACKC
21
NREQD
22
NACKD
20
Decoding FIFO Decoding table
VDD
VSS
MN86062
TEST(4:0)
MN86062
Pin Descriptions System Bus Interface
Pin No. 27 28 29 30 33 34 35 36 37 38 39 40 24 25 26 23 22 21 20 32 31 46 43 15 5 2 45 16 4 1 44 41 42 17 18 19 3 Symbol A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 NWT NRD NCS NREQC NREQD NACKC NACKD NIRQ NRESET 2SYSCLK SYSCLK VDD4 VDD3 VDD2 VDD1 VSS4 VSS3 VSS2 VSS1 TEST4 TEST3 TEST2 TEST1 TEST0 TACK O Do not use these test pins. I Do not use these test pins. I I I I O Tristate O Tristate I I O Open drain I I O I I/O Tristate I/O I
For Communications Equipment
Function Description Address bus for accessing internal registers
Data bus for bidirectional transfers over system bus
Connect to WR pin on X80-compatible microprocessor Connect to RD pin on X80-compatible microprocessor Chip select pin This output pin indicates a DMA transfer request from the 86062 to memory. This output pin indicates a DMA transfer request from the memory to 86062. This input pin accepts the response to the NREQC signal. This input pin accepts the response to the NREQD signal. This output pin indicates an interrupt request. External input resets the 86062. This input pin accepts a clock signal with twice the system clock frequency. This output pin provides a clock signal with half the frequency of 2SYSCLK. Connect these power supply pins to a 5 volt power supply.
Connect these power supply pins to ground.
For Communications Equipment
Pin Descriptions (continued) Image Bus Interface (continued)
Pin No. 59 60 61 62 63 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 7 8 9 10 11 12 13 14 47 48 50 51 Symbol IA23 IA22 IA21 IA20 IA19 IA18 IA17 IA16 IA15 IA14 IA13 IA12 IA11 IA10 IA9 IA8 IA7 IA6 IA5 IA4 IA3 IA2 IA1 IA0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 IBREQ IBACK IAEN IR/W O I O Tristate O Tristate I/O Tristate Image data bus for bidirectional transfers of image data I/O O Tristate
MN86062
Function Description Image address bus. The address is valid when the NIAEN pin is at "L" level.
This output pin indicates a request for control of the image bus. This input pin accepts the response to the NIBREQ signal. This output pin indicates whether the values of image address bus are valid. This output pin indicates the data transfer direction for the image bus.
MN86062
Pin Descriptions (continued) Image Bus Interface (continued)
Pin No. 52 49 57 58 53 54 55 56 Symbol IDACK DRUN DEND DCMP DREQ0 DREQ1 DACK0 DACK1 I/O I O Tristate O O I I O O
For Communications Equipment
Function Description This input pin indicates the end of a data read or write operation. This output pin indicates whether a DMA transfer is in progress. This output pin indicates the end of a DMA cycle. This output pin indicates successful completion of a DMA block transfer. This input pin indicates a DMA transfer request from the I/O block to memory. This input pin indicates a DMA transfer request from the memory to I/O block. This output pin gives the response to the NDREQ0 signal. This output pin gives the response to the NDREQ1 signal.
Test Pin Setting
Symbol TEST0 TEST1 TEST2 TEST3 TEST4 Pin No. 19 18 17 42 41 Fixed Level GND GND GND GND GND
For Communications Equipment
Package Dimensions (Unit: mm)
QFP084-P-1818
MN86062
22.900.40 18.000.20 63 43 42 (1.00) 18.000.20 84 22 1 (1.00) 0.80 21 2.90 max. 2.500.20 0.350.10 (2.450.20)
+0.10 -0.05
64
0.15
22.900.40
0.100.10
0 to 10 (1.300.20)
0.15
SEATING PLANE

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